Conventionally, to shorten the time and reduce the costs involved in designing and developing of system Large Scale Integrations (LSIs), macros are created by modularizing commonly-incorporated electronic circuits. Examples of hard Intellectual Properties (IPs) obtained by modularizing hardware such as an electronic circuit include a Central Processing Unit (CPU) macro obtained by modularizing a CPU and a Random Access Memory (RAM) macro obtained by modularizing a RAM.
In recent years, because logic functions and circuit configurations have been getting complicated due to the endeavor to lower electric power consumption and to provide more advanced functions, it is difficult to realize higher-speed processing with RAM macros. Consequently, RAM macros devised with a variety of ideas are known.
For example, a configuration is disclosed in which a redundant cell array is provided for each of cell array blocks that each represent an area of memory cell arrays in which bit lines and word lines are arranged next to one another. More specifically, in the disclosed configuration, redundant column cell arrays are arranged in the column direction of the cell array blocks, whereas redundant row cell arrays are arranged in the row direction of the cell array blocks, so that the redundant column cell arrays and the redundant row cell arrays are used in combination.
As another method for achieving high-speed processing, a method has been used by which bit lines are divided, as illustrated in a memory cell configuration in FIG. 5, for example. In the memory cell configuration illustrated in FIG. 5, a redundant cell array is provided for each of cell arrays that each include a plurality of memory cells that are connected to bit lines such as BLn and /BLn (where “n” denotes the quantity of memory cells, whereas “/” denotes negativity) and connected to word lines such as WL0, WL0d, WL1, and WL1d. Further, by providing a dummy cell array between the cell arrays, the bit lines between the cell arrays are divided so as to reduce the load on the bit lines and to make the speed of the processing higher. FIG. 5 is a diagram of the conventional configuration of the memory cells.
Patent Literature 1: Japanese Laid-open Patent Publication No. 2000-294748
Patent Literature 2: Japanese Laid-open Patent Publication No. 2003-178594
Patent Literature 3: Japanese Laid-open Patent Publication No. 2004-055094
According to the conventional technique, however, the number of sections into which the cell arrays are divided increases, as the speed of the RAM macro is made higher and as the capacity of the RAM macro is made larger. As a result, problems arise where a large proportion is accounted for by the redundant cell arrays provided for the cell arrays and by the dummy cell array used for dividing the bit lines and where the macro area size becomes larger. In other words, according to the conventional technique, although a high-speed operation and redundancy efficiency of the RAM macro are maintained, it is difficult to keep the RAM macro compact because the area sizes of the redundant cell arrays and the dummy cell array are large.
Further, as illustrated in FIG. 6, bit line contacts used for connecting bit lines and memory cells together are arranged in cell-end positions of the memory cells. Because each of the bit line contacts is shared by adjacently-positioned memory cells, it is not possible to divide the bit lines at the cell-end positions of the memory cells. Accordingly, in order to maintain the continuity of the memory cells, the dummy cell array that divides the bit lines is used to have an area size equal to at least one memory cell. As a result, the RAM macro area size increases. FIG. 6 is a diagram for a memory cell layout of a six-transistor Static Random Access Memory (SRAM).